Shift register operated calculating machines

ABSTRACT

An electronic calculating machine with at least two multistage registers capable of subtraction, with the digits of the subtrahend and minuend aligned, has a circuit for controlling the shift of one register relative to the other in response to receipt of a predetermined plurality of electronic shift pulses controlled by an arithmetic function circuit to shift the highest denomination stage of one register and to vary the number of shift pulses applied to both registers.

United States Patent [451 Jan.25,i972

Drage [54] SHIFT REGISTER OPERATED CALCULATING MACHINES [72] Inventor: James John Drage, Uxbridge, Middlesex,

England [73] Assignee: Sumlock Anita Electronics Limited, Middlesex, England- [22] Filed: July 18, 1969 21] Appl. No.: 843,138

301 Foreign Application Priority Data July 18, 1968 Great Britain ..34,3l4/68 [52] US. Cl ..235/l60, 235/168 [51 Int. Cl. ..G06f 7/385 [58] Field ofSearch ....235/159,l60,168,176

[56] References Cited UNITED STATES PATENTS Primary Examiner-Charles E. Atkinson Attorney-Laurence R. Brown I 57] ABSTRACT An electronic calculating machine with at least two multistage registers capable of subtraction, with the digits of the subtrahend and minueud aligned, has a circuit for controlling the shift of one register relative to the other in response to receipt of a predetermined plurality of electronic shift pulses controlled by an arithmetic function circuit to shift the highest denomination stage of one register and to vary the number of shift pulses applied to both registers.

13 Claims, 14 Drawing Figures earn-m SHIFT REGISTER OPERATED CALCULATING MACHINES This invention has reference to calculating machines and has particular reference to a calculating machine with at least two registers having a circuit for controlling the shift of one register with respect to the other register.

In calculating machines having at least two registers it is essential during arithmetic calculations to add and subtract the same denominations. Thus, for example, in carrying out an addition operation it is essential that the unit digit of the first addendum is added to the unit digit of the second addendum and the tens digit of the first addendum is added to the tens digit of the second addendum, etc.

Similarly, it is essential in carrying out a subtraction operation to have the unit and other respective digits of the minuend and subtrahend entered into the registers in an aligned manner.

An object of the invention is to provide an improved calculating machine.

A further object of the invention is to provide a calculating machine with at least two registers havinga circuit for controlling the shift of one register with respect to the other register.

According to the present invention there is provided a calculating machine having at least two multistage registers which are supplied with pulses from a source of shift pulses and having a circuit for controlling the shift of one register with respect to the other register, said control circuit comprising a shift pulse control circuit for varying the number of shift pulses supplied to one of the registers, an addition circuit for adding a digit or the complement of the digit in a stage of one of the registers to a digit in a stage of the other register, and an arithmetic function control circuit for controlling the shift pulse control circuit and the addition circuit; whereby, when the arithmetic function control circuit operates the shift pulse control circuit and not the addition circuit, the shift pulse control circuit varies the number of shift pulses supplied to each of the registers so that the highest denomination stage of one register is successively shifted in one direction with respect to the highest denomination stage of the other register and the shift pulse control circuit then varies the number of shift pulses applied to each of the registers so that the highest denomination stage of the one register is successively shifted in the opposite direction to the one direction; and whereby, when the arithmetic function control circuit is operated to control an arithmetic operation to be performed by the calculating machine, the shift pulse control circuit is operated to supply equal numbers of shift pulses to the register while the addition circuit is operated to add a digit or the complement of a digit in one register to a digit in the other register at a relative shift position dependent upon the arithmetic operation to be performed by the calculating machine.

A constructional embodiment made in accordance with the invention will now be described, by way of example with reference to the accompanying drawings wherein:

FIGS. 1 and la shows a block diagram of part of an electronic calculating machine made according to the invention;

FIG. 2 shows the set of gates 48 shown in FIG. I in greater detail;

FIG. 3 shows the set of gates 34 shown in FIG. I in greater detail;

FIG. 4 shows part of the set of gates 58 shown in FIG. 2 in greater detail;

FIG. 5 shown part of'the set of gates 22 shown in FIG. I in greater detail;

FIG. 6 shows part of the set of gates 50 shown in FIG. I in greater detail;

FIG. 7 shows part of the set of gates 36 shown in FIG. 1 in greater detail;

FIG. 8 shows part of the set of gates 76 shown in FIG. 1 in greater detail;

FIG. 9 shows part of the set of gates 72 shown in FIG. I in greater detail;

FIG. 10 shows part of the set of gates 11 shown in greater detail;

FIG. 11 shows part of the set of gates 54 shown in FIG. I in greater detail;

FIG. 12 shows part of the set of gates 68 shown in FIG. I in greater detail; and

FIG. 13 shows part of the set of gates 64 shown in FIG. I in greater detail.

The FIG. I shows an electronic calculating machine made according to the present invention. In FIG. I a master oscillator l generates free-running oscillator pulses GD which are on at |+l2 v. and off" at 0 v. The oscillator I is connected to an input decade 2 which is connected as a Johnson ring circuit. The input decade 2 divides the master oscillator pulses GD into sequential groups of 10 pulses, viz. PI), P1, P2, P3, P4, P5, P6, P7, P8 and P9. The output pulses P0 to P9 from the input decade 2 are internally gated to give waveforms P0, P5 and P9, a waveform 9, and a shift pulse waveform (1P9.

Waveform P0" is up (at +12 volts) from the back edge 0 the P9 pulse to the back edge of the P0 pulse.

Waveform P5 is up from the back edge of P4 pulses to the back edge of P5 pulse.

Waveform P9 is up from the back edge of P8 pulse to the backedge of P9 pulse.

Waveform 9" is up from the back edge of P0 pulse to the back edge of P9 pulse.

Waveform dP9 is up from the back edge of P9 pulse to the front edge of P0 pulse.

The calculating machine has a digit keyboard 5 having l0 normally open digit key switches (not shown) representing the digits 09 respectively, which switches are closed when the corresponding keys (not shown) are depressed. The normally open contact of the digit key switches (not shown) representing the digits 0-9 respectively are connected to the pulses P9 to P0 respectively and the connections to the movable contact of the digit key switches are connected to a digit gate circuit 7 which has an output to a digit highway HW2. When a digit key (not shown) is depressed to close the corresponding digit key switch, a train of pulses of number equal to the digit corresponding to the digit key depressed is repetitively transmitted along the digit highway HWZ until the depressed digit key is released.

The calculating machine also has a function keyboard 8 which has function key switches (not shown) marked with the following symbols X," decimal point, constant," and enter. The function key switches (not shown) marked X and which control the arithmetical functions of addition, subtraction, multiplication, and division respectively, are similar to the digit key switches and are connected in a similar way to a function gate circuit 9. The output from the function gate circuit 9 is connected to a function highway HW3. When a function key is closed by depression of the function key, the corresponding function signal is transmitted along the highway I-IW3. The four function signals transmitted along the highway HW3 are:

on depression of the key, up at the back edge of P7, down at the back edge of P0;

on depression of the key, up at the back edge of P7, down at the back edge of P0;

on depression of the X key, up at the back edge of P3, down at the back edge of P0;

on depression of the key, up at the back edge of P5, down at the back edge of P0;

The minus key also puts a minus signal M to the logic gates. The keys marked decimal point," enter" and constant" are connected to a source of positive potential.

The entry key transmits a CE signal along the line C.E., when the entry key is depressed. The decimal point key transmits a DP" signal along the line D.P., when the decimal point key is depressed; and the constant transmits a constant signal K" along the line K, when the constant key is depressed.

A function counter circuit 10 is a decade counter internally interconnected to count up to eight. An output is connected to a respective count state and the eight outputs are labeled in order of ascending count state as the function positions F0, F1, F2, F3, F4, F5, F6 and F7 respectively. The function position F is connected to an inverter circuit 10a to give and output F 0. The function position F0 is also connected to a delay circuit 10b to give an output dFO which comes up at the back edge of the pulse from the function position F0 and goes down the back edge of the next T pulse. The input of the function counter circuit is connected by a highway HW4 to a set of gates 11. The outputs of the function positions F0 to F7 and dFO are connected to the input ofa respective emitter follower of a group of nine emitter followers which are shown as the rectangles 100 in FIG. 1.

The outputs of the respective emitter followers are connected to the logic gates which are controlled by the respective function position.

The functions controlled by the function positions are:

FO-display of wait Flclear F2index F4subtract F5-divide F6-not used F7-multiply A timer circuit 12, which is a seven-position Johnson ring circuit is internally interconnected to have 13 count stages which are labeled in order of ascending count states T0, TD, T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11. The timer circuit 12 is driven continuously by 10th or P9 pulses from the input decade 2 so that the count stage outputs are sequentially and continuously generated and each count state output lasts from the back of the P9 pulse to the back edge of the next P9 pulse.

A visual display 14 includes 10 number tube circuits each having a number tube 16 and I0 decimal point neon bulbs 17. The anodes ofthe number tubes 16 are connected in sequence to a positive potential under the control of the outputs T10 to T1 respectively of the timer circuit 12. The highest significant digit in a displayed number is positioned in the left-hand number tube, which is controlled by the output T10.

One connection to each of the neon bulbs 17 is connected together and these are connected to the output TD of the timer circuit 12. The cathodes of the 10 number tubes 16 which are shaped to the same digit are connected together. The other connection of the neon bulb 17 at the left-hand side of FIG. 1 is connected to the connected together cathode connections for the digit zero, the other connection of the next neon bulb being connected to the cathode connections for the digit one and so on until the other connection of the lOth neon bulb 17 is connected to the cathode connections for the digit nine.

The 10 bunched cathode connections are connected to the outputs of a row of bistables which form a staticizer 18. The inputs of the staticizer 18 are connected to the outputs of a buffer 20 in form of a decade counter which is internally interconnected so as to convert a train of pulses into the binarycoded decimal equivalent which appears on the output of the decade counter. The input of the buffer 20 is connected by a highway HW8 to the output ofa set of gates 22. The contents of the buffer 20 is cleared from the buffer 20 into the staticizer 18 at the front edge of each P0 pulse and the staticizer 18 is cleared, i.e., the digit zero line is energized, at the back edge of each P9 pulse. The buffer 20 has an output B0 which is energized, i.e., goes to a positive potential, when the buffer 20 stores a digit zero, so that the number cleared from the buffer 20 stays in the staticizer 18 for nearly the duration of an output from the timer circuit 12. The buffer output B0 is connected to an inverter circuit 20a to produce an inverted output W.

The number tube 16 connected to the output T2 of the timer circuit 12 displays the units digit, the number tube 16 connected to the output T3 displays the tens digit and so on. The position of the decimal point is given by a train of pulses loaded into the buffer 20 when the output TD of the timer circuit 12 is energized and is entered into the staticizer 18 and is displayed by the neon bulb 17 at the position corresponding to the number of pulses in the train, when the next output T1 of the timer circuit is energized. Similarly if for example the digit four is to be displayed at the tens position, a train of four pulses is entered into the buffer 20 when the output T2 of the timer circuit is energized and the binary-coded decimal equivalent of the digit four appears on the output ofthe buffer 20. This binary-coded decimal output is transferred from the buffer 20 to the staticizer 18 at the pulse P0 and the digit four is displayed on that number tube 16 which is switched on when the output T3 of the timer circuit 12 is energized. The digit four is cleared from the staticizer 18 when the pulse P9 occurs at the end of the time in which the output T3 is energized. The frequency at which the outputs from the timer circuit 12 is energized is such that the digits appearing on the number tubes 16 and the decimal point appearing on a neon bulb 17 appear to be stationary because of the persistence effect of ocular vision.

A first input register 24 has four shift registers 25a, 25b, 25c, and 25d each having 12 digit stages. The input and output of the four shift register 25a, 25b, and 25d, are each connected in an endless loop with a shift register buffer 26 in the form of four bistable circuits which are internally interconnected to form a decade counter and which act as the 13th digit stage. The number of count states of the timer circuit 12 is equal to the number of stages of the input register 24. The shift pulse input to four shift registers 25a, 25b, 25c, and 25d and the shift register buffer 26 are connected by a highway HWlS to a first set of gates 34.

The set of gates 34 provide shift pulses dP9 to the four shift registers 25a, 25b, 25c and 25d and to the shift register buffer 26 so that the binary-coded decimal digits in the four shift registers circulated through the shift register buffer 26 and back to the input of the shift registers respectively.

A bistable circuit of the shift register buffer 26 has a carry pulse output which is energized when the digit in the shift register buffer 26 goes from the count of nine to the predetermined count of zero. The carry pulse output is connected to the input of a carry store 28. The carry store 28 comprises a first bistable circuit 30 having the outputs CO1 and C O l and a second bistable circuit 32 having the output CPOl. The set" connections from the first bistable circuit 30 and the second bistable circuit 32 respectively are connected to the carry pulse output of the shift register buffer 26. The first bistable circuit 30 is reset by a pulse P0 so that the output CO] is energized, ie, is at a positive potential. A carry pulse from the shift register buffer 26 causes the output CO1 to be energized. The second bistable circuit 32 is reset by a pulse P5, so that the output CPO] is not energized until a carry pulse is received from the shift register buffer 26. A set of gages 36 are connected by a highway HWS to the input of the shift register buffer 26. The carry store 28 and the set of gates 36 comprise an addition circuit of input register 24.

A second register, accumulator register 38 has four l2-stage shift registers 39a, 39b, and 39d, a shift register buffer 40 and a carry store 42 as previously described for input register 24. The shift pulse inputs of the four shift register 39a, 39b, 39c and 39d and the shift register buffer 40 are connected by a highway HW16 to a second set of gates 48. The carry pulse output of the shift register buffer 40, which is energized when the shift register buffer 40 goes through a predetermined count of zero, is connected to the input of the carry store 42 which comprises a first bistable circuit 44 having the outputs CO2 and W and a second bistable circuit 46 having an output CF02. The first bistable circuit 44 is reset by a pulse P0 so that the output CO2 is energized and the second bistable circuit is reset by a pulse P5 so that the output CF02 is not energized. The shift register buffer 40 is connected by a highway HWl to a set of gates 50. The carry store 42 and the set of gates 50 comprise an addition circuit of the accumulator register 38.

Thus in the input register 24 and the accumulator register 38 the shift registers and the shift register buffers fomi l3- stage loops around which pulse patterns circulate in synchronism with the energized outputs of the timer circuit 12. If the input register 24 or accumulator register 38 receives 13 shift pulses, the digit in the units or T1 digit stage of the input register 24 or accumulator register 38 is in the shift D0 buifer 26 or 40 respectively when the output T1 of the timer circuit 12 is energized. Similarly the th or T2 digit stage of the input register 24 or accumulator register 38 is in the shift register buffer 26 or 40 respectively when the output T2 of the timer circuit 12 is energized, and so on.

If one shift pulse to a register is suppressed, so that the register only receives 12 shift pulses, the number in the register is moved one place to the left with respect to the outputs of the timer circuit 12. i

If an extra pulse is gated into a register with the pulse PS, the number in the register is moved one place to the right with respect to the outputs of the timer circuit 12.

A slip counter 52, which is a four-bistable ripple-through counter internally interconnected to have 13 count states which are labeled in ascending order of count state S0, SD, S1 S11, has outputs to the S0 and S11 count states. The outputs to the count states S0 and S11 are connected to invertor circuits 52a and 52b respectively to give the outputs SIT and STII. The outputs S11, W1 and S8 are used to control logic circuit gates. The input of the slip counter 52 is connected by a highway I-IW6 to a set of gates 54. The slip counter 52 is driven by P9 pulses to maintain its energized count states in correspondence with the energized count state outputs of the timer circuit 12. Shift pulses are suppressed or extra ones gated in through the set of gates 54. The main purpose of the slip counter 52 is to keep a record of the amount of slip with respect to the timer circuit 12, which occurs when a number is shifted in the input register 24 or the accumulator register 38.

A decimal counter 56, which is a four-bistable ripplethrough counter internally interconnected so as to have 10 count states, has its output connected to the set input of an output bistable circuit 60. The input of the decimal counter 56 is connected by a highway HW9 to a set of gates 58. The output bistable circuit 60 has the outputs DO and W5. The output bistable circuit 60 is arranged so that the output D0 is energized when the count in the decade counter 56 goes to or passes through the zero count state; the output bistable circuit 60 is reset so that the output D 0 is energized by the next P0 pulse.

The decimal counter 56 holds the count corresponding to the position of the decimal point digit of a number stored in the accumulator register 38. This decimal point digit is held separately from the other digits in the accumulator register 38 because the accumulator register is used for calculation of products and quotients and the whole accumulator register 38 is required for holding partial products or partial remainders during the calculation. The decimal point digit is also held separately because the answer in the accumulator register 38 may need to be repositioned so as to display the most significant digit of the answer in the left-hand number tube 16 of the visual display 14, and this is more easily done if the decimal point digit is held separately.

A bistable circuit 62 having the outputs A and A has the input connected by a highway HW13 to a set of gates 64. A further bistable circuit 66 having the one output and the other output C and G respectively has the input connected by a highway HW7 to a third set of gates 68. A still further bistable circuit 70 having the one output and the other output D and 5 respectively has the input connected by a highway HWll to a fourth set of gates 72. v

A bistable circuit 74 having outputs E and E has the input connected by a highway HWIZ to a set of gates 76. A bistable circuit 78 having the outputs H and F has the input connected by a highway HW14 to a set of gates 80.

The bistable circuit 62 controls which register has its number displayed by the visual display 14: if the bistable circuit 62 is set so that output A is energized the number stored in the input register 24 is displayed; if the bistable circuit 62 is set so that the outputA is energized, the number stored in the accumulator register 38 is displayed.

The bistable circuit 66 controls the time at which the input register can shift with respect to the accumulator register so that the four basic arithmetic functions can be performed by the calculating machine. If the bistable circuit 66 is set so that the output C is energized, shift between the registers, can take place; if the bistable circuit 66 is reset so that the output G is energized the registers are held so that shift cannot take place.

The bistable circuit 70 together with the bistable circuit 66 controls the number of shift pulses sent through the set of gates 34 and 48 to the input register 24 and the accumulator register 38 respectively. This operation is to control number of shift pulses more fully described later.

The bistable circuit 74 has a control function which occurs during a multiplication operation.

The bistable circuit 78 has a control function which occurs if the number stored in the accumulator register 38 becomes negative during an addition, subtraction or display operation.

The FIGS. 2 to 13 show in greater detail, part of the some of the set of gates shown in FIG. 1. Unless otherwise indicated in the description the circuits shown are AND logic circuit gates.

The FIG. 2 shows in detail the set of gates 48 shown in FIG. 1. The set of gates 48 includes the AND" gates 480 to 487, the transistor invertor circuits 480a and 483a, the time delay circuits 482a and 485a and a circuit 487a. The circuit 487a comprises a transistor invertor circuit whose input is connected through a resistor-capacitor network to the output of an AND" gate.

The FIG. 3 shows in detail the set of gates 34 shown in FIG. 1. The circuit in the Figure comprise the AND-gates 340 to 345, the OR-gates 481a, 482a, 343a and 344a and a transistor invertor circuit 340a for the output T0 of the timer circuit 12.

The FIG. 4 shows in detail part of the set of gates 58 shown in FIG. 1. The circuits in the Figure comprise the AND-gates 582, 583, 588, 589, 591, 592 and 593, the time delay circuits 589a and 591a and an invertor circuit 592a.

The FIG. 5 shows in detail part of the set of gates 22 shown in FIG. 1. The circuits in the Figure comprise the AND-gates 222 to 226 and 231 to 233, the invertor circuits 222a and 225a and a circuit 233a. The circuit 233a shows an AND gate whose output is connected to the input of a transistor invertor and gate circuit whose output is connected to another transistor invertor and gate circuit.

The FIG. 6 shows in details part of the set of gates 50 shown in FIG. 1. The circuits in the Figure comprise the AND-gates 500, 504 to 509, 517 to 521, 523 and 524, a transistor invertor and time delay circuit 504a and the transistor invertor circuits 509a, 517a, 519a and 520a.

The FIG. 7 shows in detail part of the set of gates 37 shown in FIG. 1. The circuits in the Figure comprise the AND-gates 366 and 373.

The FIG. 8 shows in detail part of the set of gates 76 shown in FIG. 1. The circuit shown in the Figure comprises the AND- gates 760, 761, 765 and 771 and a time delay circuit 771a.

The FIG. 9 shows in detail part of the set of gates 72 shown in FIG. 1. The circuits shown in the Figure comprise the AND- gates 720, 722 and 723 an OR logic gate 722a and a transistor invertor 011" gate circuit 720a.

The FIG. 10 shows in detail part of the set of gates 11 shown in FIG. 1. The circuit shown in the Figure comprises the AND- gates 116 to 118, a time delay circuit 226a and a transistor invertor circuit 118a.

The FIG. 11 shows in detail part of the set of gates 54 shown in FIG. 1. The circuit shown in the Figure comprises the AND- gates 545 to 547, the OR-gates 545a, 546a, and 547a and the transistor invertor circuit 547b.

The FIG. 12 shows in detail part of the set of gates 68 shown in FIG. 1. The circuit shown in the Figure comprises the AND- gates 685 to 691.

The FIG. 13 shows in detail part of the set of gates 64 shown in FIG. 1. The circuit shown in the Figure comprises an AND- gate 642.

When the first gate 480 of the second set of gates 48 (FIG. 2) is energized, the gate 480 supplies [2 shift pulses to the accumulator register 38 when all of the outputs of the timer circuit 12 have been energized during a timer cycle. As a result of successive timer cycles with gate 480 energized, the stages of the input register 24 are shifted in increments of a register stage with respect to the outputs of the timer circuit so that the output T11 of the timer circuit 12 successively coincides with the input register stages T11, T10, T9 T0, in 13 successive timing cycles of the timer circuit 12. Thus the suppressed shift pulse has the effect of making the accumulator register 38 move to the left with respect to the outputs of the timer circuit 12.

The first gate 480 of the second set of gates 48 supplies l2 shift pulses dp9 to the accumulator register 38, and the second gate 487 supplies the 13th shift pulse if the input E is energized, so that the shift pulse to the accumulator register 38 and the outputs ofthe timer circuits 12 occur in synchronism.

When one of the gates 481 to 486 is energized, a shift pulse occurs at the time of the pulse PS. If this shift pulse occurs when the gates 480 and 487 (FIG. 2) are energized, 14 shift pulses are supplied to the accumulator register 38 when all of the 13 outputs of the timer circuit 12 have been energized during a timer cycle so that, as a result of successive cycles, the stages of the accumulator register 38 are shifted in increments of a register stage with respect to the outputs of the timer circuit 12. The extra shift pulse has the effect of making the accumulator digits shift to the right with respect to the outputs of the timer circuit 12.

Similarly, the first gate 340 of first set of gates 34 (FIG. 3) supplies 12 pulses to the input register 24 and makes the input register 24 shift to the left with respect to the outputs of the timer circuit 12. The gates 341, 343 or 344 supply a shift pulse which, when supplied with the 12 pulses from the gate 340, causes the stages of the input register and the outputs of the timer circuit to move in synchronism. The gates 342 or 345 add an extra shift pulse which occurs at the time of the pulse P which, when supplied with the 13 shift pulses from the gate 340 and the gate 341, 343 or 344, causes the data in the stages of the input register to shift to left with respect to the outputs of the timer circuit 12. The number of shifts of the input register 24 in one direction is equal to the number of shifts in the other direction. The number of shifts in both directions is not more than the number of stages in the register having the least number of stages. The first set of gates 34 and the second set ofgates 48 comprise a shift pulse control circuit.

The shift pulse control circuit is built into the calculation machine so that the number in the input register 24 is shifted relative to the number in the accumulator register 38. This shift pulse control circuit is used to perform a shift routine during the routine arithmetic functions of addition, subtraction, multiplication or division is performed. The shift pulse control circuit is controlled by an arithmetic function control circuit which includes the first bistable circuit 66 and the second bistable circuit 70.

During the shift routine the input register 24 starts at an initial condition in which the highest denomination stage of the input register 24 and the highest denomination stage of the accumulator register 38 are in step. The input register 24 is then shifted a stage a time to the right with respect to the accumulator register 38 until the highest denomination stage of the input register has shifted I 1 stages to the right. The input register is then shifted a stage at a time to the left until the highest denomination stages of the input register and the accumulator register are again in step. The arithmetic function of division takes place during the right shift; the arithmetic function of multiplication takes place during the left shift. The arithmetic function of addition or subtraction occurs after a repositioning shift to align corresponding denomination. The addition and subtraction routines have a repositioning shift and an addition operation in place of the right shift. At the initial (and final) condition of the registers each register received l3 shift pulses during a timing period of the timer circuit 12, i.e., one shift pulse each time a timer output is energized, by

means of the gates 480 and 487 (FIG. 2) connected to the accumulator register 38 and the gates 340 and 343 (FIG. 3) connected to the input register 24. The slip counter 52 moves in step with the input register 24, so that the output S11 from the slip counter is coincident with the output T11 from the input register, by means of the gates 546 and 547 (FIG. 11), When the bistable circuits 66 and 70 (FIG. 1) are set so that the outputs C and D respectively are energized, the gates 342 and 545 add a 14 shift pulse P5 to the input register 24 and the slip counter 52 respectively at each time cycle to slip the input register to the right by one stage with respect to the accumulator register. The output S11 of the slip counter 52, which was initially coincident with the output T11 of the timer circuit, is slipped in succession to be coincident with the outputs T10, T9, T8, T7, T6, T5, T4, T3, T2, TD, T0 after successive cycles of the timer circuit 12. After 1 1 cycles of the timer circuit 12, the input register has slipped l 1 stages with respect to the accumulator register so that the output S11 and TD are coincident to energize the changeover gate 722 which pulses the bistable circuit 70 so that the other output 5 is energized. Because the output 15 of the bistable circuit 70 is energized, the gates 342 and 343 of the input register and the gates 545 and 546 of the slip counter 52 are closed so that only 12 shift pulses are passed to the input register and the slip counter 52 while 13 shift pulses are passed to the accumulator register 38. The input register and the slip counter slip to the left with respect to the accumulator register so that after 1 l cycles of the timer circuit the output S11 of the slip counter is coincident with the output T11 of the timer circuit so that eventually the gate 118 causes the answer stored in the accumulator register 38 to be displayed on the visual display 14. During the shift routine the input register 24 is held at any position of shift with respect to the accumulator register by setting the bistable circuit 66 so that the output 6 is energized as hereinafter described.

In the multiplication operation the number in the accumulator register 38 is the multiplier and the number in the input register is the multiplicand. The product is stored in the accumulator register 38.

In the multiplication operation, depression of the multiply key puts a long pulse P4 to P0 inclusive onto the highway I-IW3. The gate 116 pulses the function counter 10 so that the function counter is driven off the output F0 after a delay of 10 milliseconds to allow for key bounce. The gate 117 pulses the function counter 10 so that the output F7 is energized. The multiplication operation occurs during the left shift. The gate 720 energizes the output D of the bistable circuit 70 when the multiply key is released so that the multiplication operation is started. the multiplication operation consists of entering the tens complement of the least significant digit in the accumulator register 38 into the buffer 20 by means of the gate 231. The gate 690 stops the left shift by energizing the output C'of the bistable circuit 66. The number in the input register 24 is added into the accumulator register 38 by means of the gates 523 and 524 and on each addition the number in the buffer 20 is increased by one increment by means of the gate 232. When the buffer 20 reaches the zero count state, i.e., B0 is energized, after a number of additions equal to the least significant figure originally in the accumulator register, the gate 691 restarts the left shift by energizing the The C of the bistable circuit 66. The input register 24 shifts one place to left and the tens complement of the next highest significant digit of the number in the accumulator register 38 is entered into the buffer 20 to repeat the sequence previously described.

This sequence is repeated until the product has been built up in the accumulator register 38 by successive addition of partial products. At the end of the multiplication operation the decimal point position of the product is calculated by adding the multiplicand decimal point count to the multiplier decimal point count stored in the decimal point counter 56 by means of the gate 593. The gate 118 then energizes the output F0 of the function counter circuit so that the answer is displayed.

1f the highest significant figure of the product or partial product spills into the T11 digit stage of the accumulator, when the T11 digit stage is energized the signal B and the signal C02 are together energized so that the gate 760 is energized by the outputE. The output E is an input to the gate and as a result of the energizing of output E by the gate 485 passes the l4th shift pulse to the accumulator register 38 to cause the accumulator register to shift one digit stage to the right so that the highest significant figure is moved into the T digit stage.

In the division operation, the number in the accumulator register 38 is the dividend and the number in the input register 24 is the divisor. The quotient is stored in the accumulator register. The division operation takes place while the input register 24 is successively shifted to the right with respect to the accumulator register 38.

The division operation will now be briefly described so that the detailed description which follows can be more easily understood.

The division operation is an alignment operation which is used to fulfill a condition that the T11 digit stage of the accumulator register 38 enters a zero digit into the buffer 20. This condition is fulfilled by causing the accumulator register to shift one stage to the right every time the nonzero signal m of the buffer is energized. When the T11 state enters a zero digit into the buffer 20, the buffer 20 receives a single pulse so that the output B0 of the buffer is energized and the division operation for calculating the quotient can begin. The usual division operation is employed in which the divisor is successively subtracted from the dividend and one digit is added to the quotient for each subtraction which does not send the remaining dividend into the negative state. The divisor is subtracted from the dividend by adding the tens complement of the divisor to the dividend. The tens complement of the divisor is calculated by adding the digit one to the nines complement of the divisor so that the recurring nines of the nines complement are changed to recurring zeros and the least significant nonzero digit of the nines complement is increased by one. If, when the tens complement of the division is added to the dividend, the addition of the highest significant digit of the tens complement to the digit of the dividend aligned with it adds up to a number of ten or more, a carry pulse is generated. The appearance of the carry pulse signifies that the dividend left after the addition of the tens complement in the positive state so that a further addition may be possible. If the addition of the highest significant digit of the divisor complement to the digit of the dividend aligned with it adds up to a number less than 10, a carry pulse is not generated and signifies that the dividend left after the addition of the divisor complement is in the negative state so that the last addition was one too many. The carry pulse which appear as a result of these addition operations are transferred to the next higher stage of the accumulator register and form a digit of the quotient. Thus each addition which results in a carry pulse adds a digit to the quotient stage in the next higher stage of the accumulator register. In the case of the first digit of dividend in the digit stage T10 of the accumulator register 38, any carry pulses would be entered in the digit stage T11 of the accumulator register 38. The appearance or nonappearance of the carry pulse is used to control the addition of the modified complement of the divisor to the dividend by entering the carry pulse into the buffer 20. At the beginning of the addition operation the buffer 20 is set by the entry of a single pulse S0 that the output fit) of the buffer is energized. During each timing cycle of the timer circuit 12 in which an addition operation takes place the buffer 20 received nine pulses. If the addition leaves the dividend left after the addition in the positive state, a carry pulse is entered into the buffer making an entry of 10 pulses which leaves the single pulse in the buffer 20 so that the output B0 of the buffer remains energized and a further addition can take place. However, if the addition leaves the dividend left after the addition in the negative state, only the nine pulses are entered into the buffer 20 so that with the single pulse already entered in the buffer a count of 10 is entered and the output B0 is energized. When the output B0 of the buffer 20 is energized, the divisor is added back into the dividend to return the dividend back to the number before the addition of the last divisor complement and the input register 24 shifts to the right by one digit stage to repeat the addition operations. The sequence of successive addition until the buffer signal B0 is energized adding back and then shifting right is repeated until 10 digits of quotient have been built up. The input register 24 then shifts left to bring the input register back to the initial relationship with the accumulator register 38. The decimal point of the quotient is calculated and then the quotient is displayed on the visual display 14. A division operation is initiated by depressing the divide" key on the function.

keyboard 8 which puts a long pulse P6 to P0 on the function highway HW3. The gate 642 causes the output A of the bistable circuit 62 to be energized and the gate 720 causes the output D of the bistable circuit to be energized. The gates I16 and 117 pulse the function counter circuit 10 so that the out put F5 is energized. The gate 760 causes the output Fof the bistable circuit to be energized which energizes the gate 366 so as to circulate the digits stored the input register 24. The gate 685 energizes the output 6 of the bistable circuit so as to prevent shift between the input register 24 and the accumulator register 38.

A situation may occur at the beginning of the division operation in which the first digit of the divisor is some way down the input register. In this situation the calculating machine would begin to try to calculate a first digit of quotient which might be greater than the correct value as a result of adding digits of quotient to any nonzero digit left in the T11 stage of the accumulator. The calculating machine is protected from this situation by an initial condition which requires that the T11 stage of the accumulator, which stores the first digit of the quotient, is zero at the beginning of the division operation.

As a result of the effects of the delay signals dF0 on the gates 685 and 760 on various circuits, the gate 223 enters the digit of the T11 stage into the buffer 20 at the beginning of the division operation. It is assumed that the T11 digit is zero so that the output B0 of the buffer 20 is energized and the initial condition is satisfied. At the beginning of the division operation a timing cycle of the timer circuit 12 is carried out with the output C of the bistable circuit 66 energized to prevent relative shift between the input register 24 and the accumulator register 38. When the timer output TD is energized the gates 224 and 226 add a single pulse and nine pulses respectively to the buffer 20 so that the count in the buffer is circulated to its original value and the output B0 of the buffer circuit remains energized. When the timer outputs T1 to T10 inclusive are energized, the gates 504 and 505 add the tens complement of the divisor to the dividend, and any carries from one digit stage are transferred to the next higher digit stage by the gate 508. If, when the highest significant digit of the dividend in the digit stage T10 is added to the highest significant digit of the tens complement of the divisor in the digit stage T10, a carry is generated, this carry is transferred to the digit stage T11 of the accumulator register as a digit of quotient by the gate 509 and this carry is entered into the buffer 20 by the gate 225 so that the buffer count stores the single pulse and the output F6 is-energized. The timer outputs T11 and T0 are energized and when the timer output TD is energized, the previously described timer cycle is followed, if a carry pulse occurs when the highest significant digits of the divisor and the remaining dividend are added together so that a second digit of quotient is added to the T11 stage of the accumulator register. However, when the addition of the highest significant digits of the dividend and the complement of the divisor do not generate a carry, the dividend remaining has gone into the negative state and the output B0 of the buffer 20 is energized to initiate the addition of the divisor to the remaining dividend and the right shift by a single digit stage of the input register 24. Thus without a carry pulse from the highest significant digit stages the output B0 of the buffer is energized so that when the timer output T11 is energized the gate 686 pulses the bistable circuit 66 so that the output C is energized in place of the output C. During the next timing cycle of the timer circuit 12, the gate 506 adds the divisor to the remaining dividend so as to restore the dividend to its previous value. At the end of the timing cycle the gate 761 pulses the bistable circuit 74 so that the output E is energized.

During the next timing cycle of the timer circuit 12, the gates 480 and 487 connected to the accumulator register 38 and the gates 340, 343 and 341 connected to the input register cause the input register to shift right by one digit stage so that the second digit of quotient will be built up in the digit stage T10 of the accumulator register. During this timing cycle the gate 223 transfers the digit in the digit stage T10, which is a zero, to the buffer 20 so that the output B is energized. At the end of this timing cycle the gate 687 pulses the bistable circuit 66 so that the output C is energized. The second digit of quotient is calculated by carries from successive cycles similar to the cycles previously described.

When a cycle does not produce a carry, the buffer output B0 is energized, and a right shift operation occurs similar to the right shift cycle previously described. When digits of quotient have been calculated, the gate 722 energizes the output D of the bistable circuit 70 to initiate the left shifts of the input register 24. After 12 left shifts which bring the input register into alignment with the accumulator register, gate 582 calculates the quotient decimal point count in the decimal counter 56 by subtracting of the divisor decimal point count from the dividend decimal point count in the decimal counter 56. Since the buffer output B0 is left energized at the end of the quotient calculation, the gate 227 pulses the buffer until the output m) is energized. The gate 118 then pulses the function counter so that the function position F0 is energized and the quotient is displayed on the visual display 14. The gate 771 pulses the bistable circuit 74 so that the outputE is energized. When the divide" key on the function keyboard 8 is released, the gate 720 sets the bistable circuit 70 so that the output D is energized.

1n the description of the division operation in the previous paragraphs it was assumed that the T11 stage of the accumulator register 38 was zero at the beginning of the division operation. Cases may occur where a division operation is initiated after a previous calculation has left a nonzero digit in the T11 stage. In this case the output W of the buffer 20 is energized when the gate 223 enters the T11 digit into the buffer 20. The gate 481 causes the accumulator register 38 to be shifted to the right by one stage so the digit originally in the T11 stage is now in the T10 stage and the gate 583 causes a pulse to be added to the decimal point counter 56 so as to correct the decimal point position by means of the gate 688. The gate 507 clears the T11 digit to zero.

During a division operation, the least significant digits of the divisor are dropped off" as the divisor in the input register is shifted to the right. If the first digit or highest significant digit of divisor is some distance down the input register, then near the end of the division calculation the divisor will be reduced to zero. As a result of a zero divisor, the remaining dividend cannot be sent negative and the calculating machine would jam. This jamming is prevented by the gate 233a which detects a zero divisor and energizes the input ZD to the gate 233 which gate drives extra pulses to the buffer 20 to zero it to complete the calculations.

In the addition operation the number in the input register 24 is added to the number in the accumulator register 38. The function counter is pulsed so as to energize the output F3 by the gates 116 and 117.

The addition operation begins with the following outputs energized; bistable circuits outputs A or A, C, D, E and F; slip counter output 511; function counter output F3; timer circuit output T0 and input decade output P0.

The first stage of the addition operation is to align the numbers in input register 24 and the accumulator register 38 so that, in effect, the decimal point counts are the same. This alignment is done by subtracting the input register decimal point count from the accumulator register decimal point count in the decimal counter 56 by means ofthe gate 588. The output of the bistable circuit 60 is energized in accordance with which register has the greater decimal point count. If the decimal point count of the accumulator register is greater than the decimal point counter of the input register (Case 1), the energized output of the output bistable circuit 60 is changed from the output D 0 t0 the output D0 and a pulse count which is equal to the difference between the decimal points is stored in the decimal counter 56. 1f the decimal point count of the input register 24 is greater than the decimal point count of the accumulator register 38 (Case 2), the energized output of the output bistable circuit 60 remains unchanged at m and a count equal to the tens complement of the difference between the decimal points is stored in the decimal counter 56.

When the accumulator register decimal point is greater than the input register decimal point (case 1), each time the output TD of the timer circuit 12 is energized the gate 765 sets the bistable circuit 74 so that the output 13 is energized and, because in this condition the output D0 is energized, when the next timer output, the output T1, of the timer circuit is energized the pulse P0 sets the output bistable circuit 60 so that the output D6 is energized. During the next cycle of the timer circuit 12, during which the outputs To to T11 are sequentially energized, the gates 480 and 487 pass 13 shift pulses to the accumulator register 38 while the gates 340, 342 and 343 and the gates 545, 546 and 547 pass 14 shift pulses to the input register 24 and the slip counter 52 respectively, so that the input register 24 moves one digit stage with respect to the accumulator register 38. Also during the cycle of the timer circuit 12, the gate 589 causes nine pulses of the output 9 to circulate and reduce by one the count in the decimal counter 56. The cycles of the timer circuit 12 and the gates previously described are operated until the count in the decimal counter 56 is zero so that the output D0 of the output bistable circuit 60 remains energized after the application of the reset pulse P0 when the timer output T1 is energized. The second stage of the addition operation, the addition of the number in the input register 24 to the number in the accumulator register 38, follows and is described later.

When the input register decimal point is greater than the accumulator register decimal point (case 2) each time the output TD of the timer circuit 12 is energized the gate 765 sets the bistable circuit 74 so that the outputE is energized. During the next cycle of the timer circuit 12 during which the outputs T0 to T11 are sequentially energized the gates 340 and 343 and the gates 546 and 547 pass 13 shift pulses to the input register 24 and the slip counter 52 respectively and the gates 480, 482 and 487 pass 14 shift pulses to accumulator register 38 so that the accumulator register 38 moves one digit stage with respect to the input register 24. Also during the cycle of the timer circuit 12 the gate 591 causes a pulse to increase by one the count in the decimal counter 56. The cycles of the timer circuit 12 and the gates previously described are operated until the count in the decimal counter 56 is zero so that the output D0 of the output bistable circuit 60 remains energized after the application of the reset pulse P0 when the timer output T1 is energized-The second stage of the addition operation, the addition of the number in the input register 24 to the number in the accumulator register 38, follows and is described later.

The second stage of the addition operation begins when the output D0 of the output bistable circuit 60 remains energized after the application of the reset pulse P0 when the timer output T1 is energized. The gates 373, 517 and 521 control the addition of the number in the input register 24 to the number in the accumulator register 38. In effect, the stage of alignment of the numbers and the stage of addition of the numbers together form a shortened right shift operation which is then followed by the full left shift operation. At the end of the addition routine the gate 723 pulses the bistable circuit 70 so that the output D is energized and the gate 689 pulses the bistable circuit 66 so that the output D is energized. The left shift operation is used to clear the input register 24 and copy the answer in the accumulator register 38 into the cleared input register 24. The digit stage T11 of the accumulator register 38 is left in the cleared state at the end of the addition routine. If, when the numbers are added together, the accumulator Till digit stage has a carry from the T10 digit stage, the output CP02 of the carry store is energized at T11. The gate circuit 482 is energized to pass a P pulse as the 14th shift pulse to the accumulator register so as to cause the accumulator register to shift one digit stage to the right with respect to the timer circuit 12 so that the most significant digit of the number is shifted from the T11 digit stage to the T digit stage. The gate 592 is energized to pass a P0 pulse to the decimal point counter 56 so as to move the decimal point position one place to the right.

The subtraction routine is similar to the addition routine and uses the usual method of adding the nines complement of the number in the input register 24 plus one digit to the number in the accumulator register, using the gates 518, 519 and 520. The right shift operation for subtraction is identical with the right shift previously described for addition. The left shift operation is used for clearing and copying as previously described for addition. As the addition and subtraction routines are so similar when the function counter output P4 is energized, the output F3 is also energized and any addition gates not required for subtraction are closed by the F4 signal from the output of invertor circuits 483a (FIG. 2), 592a (FIG. 4) and 517a FIG. 6) whose inputs are connected to the W output.

The answer to a calculation is stored in and circulates around the accumulator register 38 and is displayed when the inputs marked F0 on gates are energized. A digit is shifted into the shift register buffer 40 of the accumulator register 38 by a dP9 pulse which occurs at the same time as the next output of the timer circuit 12 is energized. The gate 500 (FIG. 6) is energized for the outputs Tl, TD and T2 to T10 of the timer circuit 12 and allows l0 oscillator GD pulses (corresponding to the pulses P0 to P9) to circulate the digit in the shift register buffer 40. At the same time a gate 222 is shut (since the first bistable circuit 44 was reset by the first pulse P0) and does not allow oscillator GD pulses to pass into the buffer 20. When the digit in the shift register buffer 40 goes through zero, a pulse is passed to the first bistable circuit 44 and the second bistable 46 so that the outputs C02 and CP02 are energized. When the input C02 is energized the gate 222 allows a number of oscillator pulses GD equal to the digit in the shift register buffer 40 to enter the buffer 20. As previously described, the digit in the buffer 20 is cleared into the staticizer 18 at the next P0 pulse (which also resets the first bistable circuit 44) and is the digit displayed on the visual display 14.

What I claim is:

l. A calculating machine having at least two multistage shift registers having shift pulse inputs, a source of shift pulses, means supplying the shift pulses to shift said registers, a circuit for controlling the shift of one register by said shift pulses with respect to the other register comprising a shift pulse control circuit for varying the number of shift pulses supplied to one of the registers, an addition circuit for adding a digit or the complement of the digit in a stage of one of the shift registers to a digit in a stage of the other shift register, and an arithmetic function control circuit for controlling the shift pulse control circuit and the addition circuit including means operating the shift pulse control circuit and not the addition circuit to vary the number of shift pulses supplied to each of the registers so that the highest denomination stage of one register is successively shifted in one direction with respect to the highest denomination stage of the other register and also including means to vary the number of shift pulses applied to each of the registers so that the highest denomination stage of the one register is successively shifted in the opposite direction to the one direction; and means operated to control an arithmetic operation to be performed by the calculating machine by the shift pulse control circuit to supply equal numbers of shift pulses to the registers while the addition circuit is operated to add a digit or the complement ofa digit on one register to a digit in the other register at a relative shift position dependent upon the arithmetic operation to be performed by the calculating machine.

2. A calculating machine according to claim 1, wherein the shift pulse control circuit includes means to control the number of shifts of the highest denomination stage of the one register in the one direction equal to the number of shift of the highest denomination stage of the one register in the other direction; and means to assure that the number of shifts of the highest denomination stage of the one register in both the one direction and the other direction is not more than the least number of the stages in either register.

3. A calculating machine according to claim 2, wherein the one register is an input register and the other register is an accumulator register.

4. A calculating machine according to claim ll, wherein the source of shift pulses and means supplying the shift pulses include a master oscillator, an input decade counter with ID outputs and a shift pulse output which counter is connected to the output of the master oscillator and which counter divides the oscillator pulses into a continuous sequence of trains of 10 pulses which appear on the 10 outputs respectively, means in the input decade counter causing each train of pulses to be separated from the next train of pulses by a shift pulse which appears on the shift pulse output, and a timer circuit having a number of outputs equal to the number of stages in the registers, the input of the timer circuit being connected to the output of the 10th pulse from the input decade counter so that the 10th pulses of the train of 10 pulses cause the outputs of the timer circuit to be energized in continuous sequence.

5. An electronic calculating machine according to claim 4, wherein the stages of each register are connected to form an endless loop.

6. A calculating machine according to claim 5, wherein a stage of both the shift registers is internally interconnected as a decade counter to form a shift register buffer; carry pulse output carry pulse output means for each shift register buffer, means in the addition circuit including a carry store circuit for each register whose input is connected to a carry pulse output of the respective shift register buffer, means energizing the carry store circuit input in response to the digit in the shift register buffer reaching a predetermined digit value, means energizing the carry store circuit output only if said digit value is received from the respective shift register buffer; and a set of gates for each register with outputs connected to the input of the shift register buffer and with inputs connected respectively to the outputs of the master oscillator, the outputs of the input decade counter, the output of the carry store circuit and to the shift register buffer of the other register at the output from the carry store circuit.

7. A calculating machine according to claim 1, wherein the shift pulse control circuit includes means to add a number of extra shift pulses to the shift pulses supplied to the one register so as to cause a shift in the one direction and means to then suppress a number of shift pulses from the shift pulses supplied to the one register so as to cause shift in the other direction.

8. An electronic calculating machine according to claim 5 wherein the shift pulse control circuit includes a first set of gates connected to the shift pulse input of the one register; the first set of gates including a first gate having inputs connected to pulse output of the input decade counter and to all but one of the outputs of the timer circuit respectively; at least one second gate having inputs connected respectively to the arithmetic function control circuit, to the shift pulse output of the input decade counter and to the timer circuit output not connected to an input of the first gate; and a third gate having inputs connected respectively to the arithmetic function control circuit, to the shift pulse output of the input decade counter and to an output of the input decade counter; and wherein the shift pulse control circuit also includes a second set of gates connected to the shift pulse input of the other register, the second set of gates including: a first gate having inputs connected respectively to the shift pulse output of the input decade counter and to all but one of the outputs of the timer circuit; a second gate having inputs respectively connected to the shift pulse output of the input decade and to the output of the timer circuit not connected to an input of the first gate; said gates being connected in a circuit operating in response to the arithmetic function control circuit by means of the shift pulse control circuit to add extra pulses for energizing all the gates of the first set of gates and the second set of gates; and in response to the arithmetic function control circuit by means of the shift pulse control circuit to suppress pulses by energizing the first gate of the first set of gates and all the gates of the second set of gates; and in response to the arithmetic function control circuit by means of the addition circuit with the shift pulse control circuit by energizing the first gate and the second gate of the first set of gates and the second set of gates.

9. A calculating machine according to claim 8, wherein the arithmetic function control circuit includes a function keyboard including a plurality of function keys, each of the function keys being connected by one connection to an output of the input decade counter, a function gate circuit whose input is connected to the other connection of the function keys and whose output is connected to a function highway; and a circuit operating when a function key is operated to transmit through the function gate circuit a function signal representative of the operated function along the function highway.

10. A calculating machine according to claim 9, wherein the function keyboard includes at least one key connected by one connection to a source of potential.

11. A calculating machine according to claim 9, wherein the arithmetic function control circuit includes a first bistable circuit having one output and another output; a further set of gates having the outputs of the gates connected to the input of the first bistable circuit, the further set of gates comprising at least one gate having an input connected to the one output of the first bistable circuit so as to energize the other output of the first bistable circuit and having at least one gate having an input connected to the other output of the first bistable circuit so as to energize the one output of the first bistable; a second bistable circuit having one output and another output; a still further set of gates having the outputs of the gates connected to the input of the second bistable circuit, the still further set of gates comprising at least one gate having an input connected to the one output of the second bistable circuit so as to energize the other output of the second bistable circuit and having at least one gate having an input connected to the other output of the second bistable circuit so as to energize the one output of the second bistable circuit, the inputs of both the further and still further sets of gates being connected respectively to outputs from the input decade counter, outputs from the timer circuit, and outputs from the function keyboard; means providing internally generated condition signals generated under the control of the addition circuit and connecting the signals to the last said sets of gates providing thereby a circuit operable in response to signals generated by the one output of the first bistable circuit being energized in coincidence with the one output of the second bistable circuit to add extra shift pulses; and providing in response to signals generated by the other output of the first bistable circuit being energized in place of the one output of the first bistable circuit to supply an equal number of shift pulses to both the registers.

12. A calculating machine according to claim 11, wherein the further set of gates includes a changeover gate having inputs respectively connected to the one output of the first bistable circuit, the one output of the second bistable circuit, an output of the timer circuit, an output of the input decade counter and an input from the function keyboard, thereby being connected to operate after the addition of a number of extra pulses equal to the number of stages in the registers to energize the other outputof the second bistable circuit in place of the one output of the second bistable circuit.

13. A calculating machine according to claim 1, wherein the arithmetic function control circuit includes means operable so that the arithmetic operation of division can take place during the addition of extra pulses and the arithmetic operation of multiplication can take place during the suppression of pulses. 

1. A calculating machine having at least two multistage shift registers having shift pulse inputs, a source of shift pulses, means supplying the shift pulses to shift said registers, a circuit for controlling the shift of one register by said shift pulses with respect to the other register comprising a shift pulse control circuit for varying the number of shift pulses supplied to one of the registers, an addition circuit for adding a digit or the complement of the digit in a stage of one of the shift registers to a digit in a stage of the other shift register, and an arithmetic function control circuit for controlling the shift pulse control circuit and the addition circuit including means operating the shift pulse control circuit and not the addition circuit to vary the number of shift pulses supplied to each of the registers so that the highest denomination stage of one register is successively shifted in one direction with respect to the highest denomination stage of the other register and also including means to vary the number of shift pulses applied to each of the registers so that the highest denomination stage of the one register is successively shifted in the opposite direction to the one direction; and means operated to control an arithmetic operation to be performed by the calculating machine by the shift pulse control circuit to supply equal numbers of shift pulses to the registers while the addition circuit is operated to add a digit or the complement of a digit on one register to a digit in the other register at a relative shift position dependent upon the arithmetic operation to be performed by the calculating machine.
 2. A calculating machine according to claim 1, wherein the shift pulse control circuit includes means to control the number of shifts of the highest denomination stage of the one register in the one direction equal to the number of shift of the highest denomination stage of the one register in the other direction; and means to assure that the number of shifts of the highest denomination stage of the one register in both the one direction and the other direction is not more than the least number of the stages in either register.
 3. A calculating machine according to claim 2, wherein the one register is an input register and the other register is an accumulator register.
 4. A calculating machine according to claim 1, wherein the source of shift pulses and means supplying the shift pulses include a master oscillator, an input decade counter with 10 outputs and a shift pulse output which counter is connected to the output of the master oscillator and which counter Divides the oscillator pulses into a continuous sequence of trains of 10 pulses which appear on the 10 outputs respectively, means in the input decade counter causing each train of pulses to be separated from the next train of pulses by a shift pulse which appears on the shift pulse output, and a timer circuit having a number of outputs equal to the number of stages in the registers, the input of the timer circuit being connected to the output of the 10th pulse from the input decade counter so that the 10th pulses of the train of 10 pulses cause the outputs of the timer circuit to be energized in continuous sequence.
 5. An electronic calculating machine according to claim 4, wherein the stages of each register are connected to form an endless loop.
 6. A calculating machine according to claim 5, wherein a stage of both the shift registers is internally interconnected as a decade counter to form a shift register buffer; carry pulse output means for each shift register buffer, means in the addition circuit including a carry store circuit for each register whose input is connected to a carry pulse output of the respective shift register buffer, means energizing the carry store circuit input in response to the digit in the shift register buffer reaching a predetermined digit value, means energizing the carry store circuit output only if said digit value is received from the respective shift register buffer; and a set of gates for each register with outputs connected to the input of the shift register buffer and with inputs connected respectively to the outputs of the master oscillator, the outputs of the input decade counter, the output of the carry store circuit and to the shift register buffer of the other register at the output from the carry store circuit.
 7. A calculating machine according to claim 1, wherein the shift pulse control circuit includes means to add a number of extra shift pulses to the shift pulses supplied to the one register so as to cause a shift in the one direction and means to then suppress a number of shift pulses from the shift pulses supplied to the one register so as to cause shift in the other direction.
 8. An electronic calculating machine according to claim 5 wherein the shift pulse control circuit includes a first set of gates connected to the shift pulse input of the one register; the first set of gates including a first gate having inputs connected to pulse output of the input decade counter and to all but one of the outputs of the timer circuit respectively; at least one second gate having inputs connected respectively to the arithmetic function control circuit, to the shift pulse output of the input decade counter and to the timer circuit output not connected to an input of the first gate; and a third gate having inputs connected respectively to the arithmetic function control circuit, to the shift pulse output of the input decade counter and to an output of the input decade counter; and wherein the shift pulse control circuit also includes a second set of gates connected to the shift pulse input of the other register, the second set of gates including: a first gate having inputs connected respectively to the shift pulse output of the input decade counter and to all but one of the outputs of the timer circuit; a second gate having inputs respectively connected to the shift pulse output of the input decade and to the output of the timer circuit not connected to an input of the first gate; said gates being connected in a circuit operating in response to the arithmetic function control circuit by means of the shift pulse control circuit to add extra pulses for energizing all the gates of the first set of gates and the second set of gates; and in response to the arithmetic function control circuit by means of the shift pulse control circuit to suppress pulses by energizing the first gate of the first set of gates and all the gates of the second set of gates; and in response to the arithmetic Function control circuit by means of the addition circuit with the shift pulse control circuit by energizing the first gate and the second gate of the first set of gates and the second set of gates.
 9. A calculating machine according to claim 8, wherein the arithmetic function control circuit includes a function keyboard including a plurality of function keys, each of the function keys being connected by one connection to an output of the input decade counter, a function gate circuit whose input is connected to the other connection of the function keys and whose output is connected to a function highway; and a circuit operating when a function key is operated to transmit through the function gate circuit a function signal representative of the operated function along the function highway.
 10. A calculating machine according to claim 9, wherein the function keyboard includes at least one key connected by one connection to a source of potential.
 11. A calculating machine according to claim 9, wherein the arithmetic function control circuit includes a first bistable circuit having one output and another output; a further set of gates having the outputs of the gates connected to the input of the first bistable circuit, the further set of gates comprising at least one gate having an input connected to the one output of the first bistable circuit so as to energize the other output of the first bistable circuit and having at least one gate having an input connected to the other output of the first bistable circuit so as to energize the one output of the first bistable; a second bistable circuit having one output and another output; a still further set of gates having the outputs of the gates connected to the input of the second bistable circuit, the still further set of gates comprising at least one gate having an input connected to the one output of the second bistable circuit so as to energize the other output of the second bistable circuit and having at least one gate having an input connected to the other output of the second bistable circuit so as to energize the one output of the second bistable circuit, the inputs of both the further and still further sets of gates being connected respectively to outputs from the input decade counter, outputs from the timer circuit, and outputs from the function keyboard; means providing internally generated condition signals generated under the control of the addition circuit and connecting the signals to the last said sets of gates providing thereby a circuit operable in response to signals generated by the one output of the first bistable circuit being energized in coincidence with the one output of the second bistable circuit to add extra shift pulses; and providing in response to signals generated by the other output of the first bistable circuit being energized in place of the one output of the first bistable circuit to supply an equal number of shift pulses to both the registers.
 12. A calculating machine according to claim 11, wherein the further set of gates includes a changeover gate having inputs respectively connected to the one output of the first bistable circuit, the one output of the second bistable circuit, an output of the timer circuit, an output of the input decade counter and an input from the function keyboard, thereby being connected to operate after the addition of a number of extra pulses equal to the number of stages in the registers to energize the other output of the second bistable circuit in place of the one output of the second bistable circuit.
 13. A calculating machine according to claim 1, wherein the arithmetic function control circuit includes means operable so that the arithmetic operation of division can take place during the addition of extra pulses and the arithmetic operation of multiplication can take place during the suppression of pulses. 